Solving non - linear electronic packaging problems on parallel computers using domain decomposition

Miniaturisation of electronic equipment, such as those found in a notebook computer, palm held devices, cell phones etc., requires high-density packing of electronic components onto printed circuit boards (PCB). To join the interconnections, solder materials are used to bond microprocessor chips and board during assembly. In the Reflow process case, the board assembly passes through a furnace where the solder bump initially in the form of solder paste, melts, reflows, and then solidifies to bond the interconnections. A number of defects may occur during and after this process such as, respectively, bridging of the liquid solder and cracking of solder joint, chip or board. With the increasing drive towards miniaturisation and smaller pitch sizes (gap between interconnection of solder bumps), these are serious issues to industry in manufacturing and component reliability in operation. Finite Element Analysis (FEA) is used extensively in the electronic packaging community to calculate stress of solders and components, for reliability analyses [Lau93] [SYS97]. Computer simulations, together with some experiments, provides an effective design and optimization route to reducing these defects and in assessing solder and board integrity and reliability. For models to fully characterise the physical phenomena of the process that govern the integrity of the final joints requires the representing physics of: